A. I. Eissa, E. Alvarez-Fontecilla, C. Weltin-Wu, and I. Galton, “A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, accepted for publication, 2024.

Youngbin Tchoe et al., “An electroencephalogram microdisplay to visualize neuronal activity on the brain surface.,” Sci. Transl. Med.16,eadj7257(2024).

H. Tan, A. Paulk, B. Stedelin, D. Cleary, C. Nerison, Y. Tchoe, E. C Brown, A. Bourhis, S. Russman, J. Lee, K. Tonsfeldt, J. C Yang, H. Oh, Y. Ro, K. Lee, M. Ganji, I. Galton, D. Siler, S. Han, K. Collins, S. Ben-Haim, E. Halgren, S. Cash, S. Dayeh, A. Raslan, “Intraoperative application and early experience with novel high-resolution, high-channel-count thin-film electrodes for human microelectrocorticography,” in Journal of Neurosurgery, vol. 1, Sept. 2023.

S. Kim and I. Galton, “Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 11, pp. 4309-4322, Nov. 2023.

P. Asbeck et al., “Integrated Circuits for Wireless Communications: Research Activities at the University of California, San Diego: Circuits Research for Wireless Communications at the University of California, San Diego,” in IEEE Microwave Magazine, vol. 24, no. 5, pp. 30-44, May 2023.

E. Helal, A. I. Eissa and I. Galton, “DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no.12, pp. 4993-5006, Dec. 2022.

Y. Tchoe, A. Bourhis, D. Cleary, B. Stedelin, J. Lee, K. Tonsfeldt, E. Brown, D. Siler, A. Paulk, J. Yang, H. Oh, Y. Ro, K. Lee, S. Russman, M. Ganji, I. Galton, S. Ben-Haim, A. Raslan, and S. Dayeh, “Human Brain Mapping With Multithousand-Channel PtNRGrids Resolves Spatiotemporal Dynamics,” Science Translational Medicine, vol. 14, issue 628, Jan. 2022.

J. Remple, A. Panigada, and I. Galton, “An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs,” IEEE Journal of Solid State-Circuits, vol. 57, no. 2, pp. 465-479, Feb. 2022.

E. Alvarez-Fontecilla, E. Helal, A. I. Eissa, and I. Galton, “Spectral Breathing and its Mitigation in Digital Fractional-N PLLs,” IEEE Journal of Solid State-Circuits, vol. 56, no. 10, pp. 3191-3201, Oct. 2021.

E. Helal, E. Alvarez-Fontecilla, A. I. Eissa, and I. Galton, “A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL,” IEEE Journal of Solid State-Circuits, vol. 56, no.9, pp. 2711-2723, Sept. 2021.

E. Alvarez-Fontecilla, A. I. Eissa, E. Helal, C. Weltin-Wu and I. Galton, “Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 3, pp. 965-974, March 2021.

D. Kong and I. Galton, “MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3084-3098, Sept. 2020.

A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. B. Taylor and R. G. Dreslinski, “Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL,” IEEE Solid-State Circuits Letters, vol. 2, no. 12, pp. 289–292, Dec. 2019.

A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. B. Taylor and R. G. Dreslinski, “A 1.4 GHz 695 Giga RISC-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS,” Symposium on VLSI Circuits (VLSIC), 2019.

D. Kong and I. Galton, “Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 2843–2853, Aug. 2019.

D. Kong, K. Rivas-Rivera and I. Galton, “A 600 MS/s DAC with over 87dB SFDR and 77dB peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error,” IEEE Journal of Solid-State Circuits, vol. 54, no. 8, pp. 2219–2229, Aug. 2019.

I. Galton and C. Weltin-Wu, “Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 1–19, Jan. 2019.

E. Alvarez-Fontecilla, C. Venerus and I. Galton, “Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3125–3137, Oct. 2018.

D. Kong and I. Galton, “Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 2, pp. 421–433, Feb. 2018.

T. Ajayi, K. Al-Hawaj, A. Amarnath, S. Dai, S. Davidson, P. Gao, G. Liu, A. Lotfi, J. Puscar, A. Rao, A. Rovinski, L. Salem, N. Sun, C. Torng, L. Vega, B. Veluri, X. Wang, S. Xie, C. Zhao, R. Zhao, C. Batten, R. G. Dreslinski, I. Galton, R. K. Gupta, P. P. Mercier, M. Srivastava, M. B. Taylor and Z. Zhang, “Celerity: An Open-Source RISC-V Tiered Accelerator Fabric,” Symp. on High Performance Chips (Hot Chips), 2017.

E. Familier and I. Galton, “Second and Third-Order Successive Requantizers for Spurious Tone Reduction in Low-Noise Fractional-N PLLs,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2017, pp. 1–4.

J. Remple and I. Galton, “The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 1, pp. 14–23, Jan. 2017.

C. Venerus, J. Remple, and I. Galton, “Simplified Logic for Tree-Structure Segmented DEM Encoders,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 11, pp. 1029–1033, Nov. 2016.

E. Familier and I. Galton, “Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 6, pp. 836–847, Jun. 2016.

C. Weltin-Wu, G. Zhao, and I. Galton, “A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,” IEEE International Solid-State Circuits Conference (ISSCC), 2015, pp. 1–3.

C. Weltin-Wu, G. Zhao, and I. Galton, “A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion,” IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2988–3002, Dec. 2015.

C. Weltin-Wu, E. Familier, and I. Galton, “A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 8, pp. 2013–2023, Aug. 2015.

C. Venerus and I. Galton, “Quantization Noise Cancellation for FDC-Based Fractional-N PLLs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 12, pp. 1119–1123, Dec. 2015.

C. Venerus and I. Galton, “A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO,” IEEE Journal of Solid-State Circuits, vol. 50, no. 2, pp. 450–463, Feb. 2015.

C. Venerus and I. Galton, “Delta-Sigma FDC Based Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 5, pp. 1274–1285, May 2013.

G. Taylor and I. Galton, “A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB,” IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 983–995, Apr. 2013.

N. Rakuljic and I. Galton, “Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 593–602, Mar. 2013.

E. Familier, C. Venerus, and I. Galton, “A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones,” IEEE Transactions on Signal Processing, vol. 61, no. 17, pp. 4270–4283, Sep. 2013.

E. Familier and I. Galton, “A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones,” IEEE Transactions on Signal Processing, vol. 61, no. 16, pp. 4172–4180, Aug. 2013.

G. Taylor and I. Galton, “A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160dB,” Symposium on VLSI Circuits (VLSIC), 2012, pp. 166–167.

K. J. Wang and I. Galton, “A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 2, pp. 264–275, Feb. 2011.

G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2634–2646, Dec. 2010.

G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time ADC Delta-Sigma Modulator,” IEEE International Solid-State Circuits Conference (ISSCC), 2010, pp. 298–299.

N. Rakuljic and I. Galton, “Tree-Structured DEM DACs with Arbitrary Numbers of Levels,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 2, pp. 313–322, Feb. 2010.

I. Galton, “Why Dynamic-Element-Matching DACs Work,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 2, pp. 69–74, Feb. 2010.

A. Panigada and I. Galton, “A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction,” IEEE International Solid-State Circuits Conference (ISSCC), 2009, p. 162–163,163a.

A. Panigada and I. Galton, “A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3314–3328, Dec. 2009.

K. J. Wang, A. Swaminathan, and I. Galton, “Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2787–2797, Dec. 2008.

K. J. Wang, A. Swaminathan, and I. Galton, “Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL,” IEEE International Solid-State Circuits Conference (ISSCC), 2008, pp. 342–618.

K. L. Chan, J. Zhu, and I. Galton, “Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2067–2078, Sep. 2008.

K. L. Chan, N. Rakuljic, and I. Galton, “Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3383–3392, Dec. 2008.

A. Swaminathan, K. J. Wang, and I. Galton, “A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation,” IEEE International Solid-State Circuits Conference (ISSCC), 2007, pp. 302–604.

A. Swaminathan, K. J. Wang, and I. Galton, “A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation,” IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2639–2650, Dec. 2007.

A. Swaminathan, A. Panigada, E. Masry, and I. Galton, “A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion,” IEEE Transactions on Signal Processing, vol. 55, no. 11, pp. 5382–5394, Nov. 2007.

S. Pamarti, J. Welz, and I. Galton, “Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 492–503, Mar. 2007.

S. Pamarti and I. Galton, “LSB Dithering in MASH Delta-Sigma D/A Converters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779–790, Apr. 2007.

K. L. Chan, J. Zhu, and I. Galton, “A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquist band,” IEEE Symposium on VLSI Circuits (VLSIC), 2007, pp. 200–201.

J. Rode, A. Swaminathan, I. Galton, and P. M. Asbeck, “Fractional-N Direct Digital Frequency Synthesis with a 1-Bit Output,” IEEE MTT-S International Microwave Symposium Digest, 2006, pp. 415–418.

A. Panigada and I. Galton, “Digital Background Correction of Harmonic Distortion in Pipelined ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 9, pp. 1885–1895, Sep. 2006.

K. L. Chan and I. Galton, “A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching,” IEEE International Solid State Circuits Conference (ISSCC), 2006, pp. 2390–2399.

M. Y. Li, I. Galton, L. E. Larson, and P. M. Asbeck, “Nonlinearity Estimation and Spectral Regrowth Prediction of Power Amplifiers Using Correlation Techniques,” The IEEE Annual Conference Wireless and Micrwave Technology, 2005, pp. 170–173.

J. L. Ceballos, I. Galton, and G. C. Temes, “Stochastic Analog-to-Digital Conversion,” 48th Midwest Symposium on Circuits and Systems, 2005, p. 855–858 vol. 1.

S. Ye and I. Galton, “Techniques for Phase Noise Suppression in Recirculating DLLs,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1222–1230, Aug. 2004.

J. Welz and I. Galton, “A Tight Signal-Band Power Bound on Mismatch Noise in a Mismatch-Shaping Digital-to-Analog Converter,” IEEE Transactions on Information Theory, vol. 50, no. 4, pp. 593–607, Apr. 2004.

E. Siragusa and I. Galton, “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2126–2138, Dec. 2004.

S. Pamarti, L. Jansson, and I. Galton, “A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL with 1-Mb/s In-Loop Modulation,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 49–62, Jan. 2004.

M. Y. Li, I. Galton, L. E. Larson, and P. M. Asbeck, “Correlation Techniques for Estimation of Amplifier Nonlinearity,” IEEE Radio and Wireless Conference, 2004, pp. 179–182.

E. Siragusa, I. Galton, “A Digitally Enhanced 1.8 V 15 b 40 MS/s CMOS Pipelined ADC,” IEEE International Solid-State Circuits Conference (ISSCC), 2004, pp. 452 – 538, Feb. 2004.

S. Ye, L. Jansson, and I. Galton, “Techniques for In-Band Phase Noise Suppression in Re-Circulating DLLs,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2003, pp. 297–300.

S. Pamarti and I. Galton, “Phase-Noise Cancellation Design Tradeoffs in Delta-Sigma Fractional-N PLLs,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 11, pp. 829–838, Nov. 2003.

I. Galton, “Delta-Sigma Fractional-N Phase-Locked Loops”, Phase-Locking in High-Performance Systems: From Devices to Architectures (ed. Behzad Razavi), Wiley-IEEE Press, 2003.

S. Ye, L. Jansson, and I. Galton, “A Multiple-Crystal Interface PLL with VCO Realignment to Reduce Phase Noise,” IEEE International Solid-State Circuits Conference (ISSCC), 2002, vol. 2, pp. 58–401.

S. Ye, L. Jansson, and I. Galton, “A Multiple-Crystal Interface PLL with VCO Realignment to Reduce Phase Noise,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1795–1803, Dec. 2002.

J. Welz and I. Galton, “Necessary and Sufficient Conditions for Mismatch Shaping in a General Class of Multibit DACs,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 12, pp. 748–759, Dec. 2002.

J. Welz and I. Galton, “A Necessary and Sufficient Condition for Mismatch Shaping in Multi-Bit DACs,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2002, vol. 1, p. I-105-I-108.

J. Keyzer, R. Uang, Y. Sugiyama, M. Iwamoto, I. Galton, and P. M. Asbeck, “Generation of RF Pulsewidth Modulated Microwave Signals Using Delta-Sigma Modulation,” IEEE MTT-S International Microwave Symposium Digest, 2002, vol. 1, pp. 397–400.

J. Grilo, I. Galton, K. Wang, and R. G. Montemayor, “A 12-mW ADC Delta-Sigma Modulator with 80 dB of Dynamic Range Integrated in a Single-Chip Bluetooth Transceiver,” IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 271–278, Mar. 2002.

I. Galton, “Delta-Sigma Data Conversion in Wireless Transceivers,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 302–315, Jan. 2002.

A. Fishov, E. Siragusa, J. Welz, E. Fogleman, and I. Galton, “Segmented Mismatch-Shaping D/A Conversion,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2002, vol. 4, p. IV-679-IV-682.

G. Chang, L. Jansson, K. Wang, J. Grilo, R. Montemayor, C. Hull, M. Lane, A. X. Estrada, M. Anderson, I. Galton, S. V. Kishore, “A Direct-Conversion Single-Chip Radio-Modem for Bluetooth,” IEEE International Solid-State Circuits Conference (ISSCC), 2002, vol. 1, pp. 88–448.

P. Asbeck, I. Galton, K.-C. Wang, J. F. Jensen, A. K. Oki, and C. T. M. Chang, “Digital Signal Processing-Up to Microwave Frequencies,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 3, pp. 900–909, Mar. 2002.

J. Welz and I. Galton, “The Mismatch-Noise PSD From a Tree-Structured DAC in a Second-Order Delta-Sigma Modulator With a Midscale Input,” Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, 2001, vol. 4, pp. 2625–2628.

P.M. Asbeck, I. Galton, L.E. Larson, X. Zhang, M. Iwamoto, J. Hinrichs and J. Keyzer, “Digital Control of Power Amplifiers for Wireless Communications,” 31st European Microwave Conference, 2001, pp. 1-4, vol. 4, pp. 2625–2628.

P. M. Asbeck, L. E. Larson and I. G. Galton, “Synergistic Design of DSP and Power Amplifiers for Wireless Communications,” in IEEE Transactions on Microwave Theory and Techniques, vol. 49, no. 11, pp. 2163-2169, Nov 2001.

J. Welz, I. Galton, and E. Fogleman, “Simplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Converters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 11, pp. 1014–1027, Nov. 2001.

J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, and P. Asbeck, “Digital Generation of RF Signals for Wireless Communications with Band-Pass Delta-Sigma Modulation,” IEEE MTT-S International Microwave Symposium Digest, 2001, vol. 3, pp. 2127–2130 vol. 3.

J. Grilo, I. Galton, K. Wang, and R. Montemayor, “A 12 mW ADC Delta-Sigma Modulator with 80 dB of Dynamic Range Integrated in a Single-Chip Bluetooth Transceiver,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2001, pp. 23–26.

E. Fogleman and I. Galton, “A Dynamic Element Matching Technique for Reduced-Distortion Multibit Quantization in Delta-Sigma ADCs,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 2, pp. 158–170, Feb. 2001.

E. Fogleman and I. Galton, “A Digital Common-Mode Rejection Technique for Differential Analog-to-Digital Conversion,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 3, pp. 255–271, Mar. 2001.

E. Fogleman, J. Welz, and I. Galton, “An Audio ADC Delta-Sigma Modulator with 100-dB Peak SINAD and 102-dB DR Using a Second-Order Mismatch-Shaping DAC,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 339–348, Mar. 2001.

E. J. Siragusa and I. Galton, “Gain Error Correction Technique for Pipelined Analogue-to-Digital Converters,” Electronics Letters, vol. 36, no. 7, pp. 617–618, Mar. 2000.

I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 3, pp. 185–196, Mar. 2000.

E. Fogleman, J. Welz, and I. Galton, “An Audio ADC Delta-Sigma Modulator with 100 dB SINAD and 102 dB DR Using a Second-Order Mismatch-Shaping DAC,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2000, pp. 17–20.

E. Fogleman, I. Galton, W. Huff, and H. Jensen, “A 3.3-V Single-Poly CMOS Audio ADC Delta-Sigma Modulator With 98-dB Peak SINAD and 105-dB Peak SFDR,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 297–307, Mar. 2000.

E. Fogleman, I. Galton, and H. Jensen, “A Dynamic Element Matching Technique for Reduced-Distortion Multibit Quantization in Delta-Sigma ADCs,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1999, vol. 2, pp. 290–293.

E. Fogleman, I. Galton, W. Huff, and H. Jensen, “A 3.3 V Single-Poly CMOS Audio ADC Delta-Sigma Modulator With 98 dB Peak SINAD,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 1999, pp. 121–124.

E. Fogleman, I. Galton, and H. Jensen, “An Area-Efficient Differential Input ADC With Digital Common Mode Rejection,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1999, vol. 2, pp. 347–350.

E. T. King, A. Eshraghi, I. Galton, and T. S. Fiez, “A Nyquist-Rate Delta-Sigma A/D Converter,” IEEE Journal of Solid-State Circuits, vol. 33, no. 1, pp. 45–52, Jan. 1998.

H. T. Jensen and I. Galton, “A Reduced-Complexity Mismatch-Shaping DAC for Delta-Sigma Data Converters,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1998, vol. 1, pp. 504–507 vol. 1

H. T. Jensen and I. Galton, “An Analysis of the Partial Randomization Dynamic Element Matching Technique,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 12, pp. 1538–1549, Dec. 1998.

H. T. Jensen and I. Galton, “A Low-Complexity Dynamic Element Matching DAC for Direct Digital Synthesis,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 1, pp. 13–27, Jan. 1998.

W. Huff and I. Galton, “Nonuniform-to-Uniform Decimation for Delta-Sigma Frequency-to-Digital Conversion,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1998, vol. 1, pp. 365–368 vol. 1.

I. Galton, W. Huff, P. Carbone, and E. Siragusa, “A Delta-Sigma PLL for 14 b 50 kSample/s Frequency-to-Digital Conversion of a 10 MHz FM Signal,” IEEE International Solid-State Circuits Conference (ISSCC), 1998, pp. 366–367.

I. Galton, W. Huff, P. Carbone, and E. Siragusa, “A Delta-Sigma PLL for 14-b, 50 kSample/s Frequency-to-Digital Conversion of a 10 MHz FM Signal,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 2042–2053, Dec. 1998.

H. T. Jensen and I. Galton, “Yield Estimation of a First-Order Noise-Shaping D/A Converter,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1997, vol. 1, pp. 441–444.

H. T. Jensen and I. Galton, “A Performance Analysis of the Partial Randomization Dynamic Element Matching DAC Architecture,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1997, vol. 1, pp. 9–12.

I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 10, pp. 808–817, Oct. 1997.

H. T. Jensen and I. Galton, “A Hardware-Efficient DAC for Direct Digital Synthesis,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1996, vol. 4, pp. 97–100.

I. Galton, “Noise-Shaping D/A Converters for Delta-Sigma Modulation,” Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS), 1996, vol. 1, pp. 441–444.

I. Galton, D. A. Towne, J. J. Rosenberg, and H. T. Jensen, “Clock Distribution Using Coupled Oscillators,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1996, vol. 3, pp. 217–220.

I. Galton and H. T. Jensen, “Oversampling Parallel Delta-Sigma Modulator A/D Conversion,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 12, pp. 801–810, Dec. 1996.

H. T. Jensen and I. Galton, “A Robust Parallel Delta-Sigma A/D Converter Architecture,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1995, vol. 2, pp. 1340–1343.

I. Galton, “A Practical Second-Order Delta-Sigma Frequency-to-Digital Converter,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1995, vol. 1, pp. 5–8.

I. Galton, “Analog-Input Digital Phase-Locked Loops for Precise Frequency and Phase Demodulation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 10, pp. 621–630, Oct. 1995.

I. Galton and H. T. Jensen, “Delta-Sigma Modulator Based A/D Conversion Without Oversampling,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 12, pp. 773–784, Dec. 1995.

I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 12, pp. 763–772, Dec. 1995.

E. King, F. Aram, T. Fiez, and I. Galton, “Parallel Delta-Sigma A/D Conversion,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 1994, pp. 503–506.

I. Galton, “Higher-Order Delta-Sigma Frequency-to-Digital Conversion,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1994, vol. 5, pp. 441–444.

I. Galton, “Granular Quantization Noise in a Class of Delta-Sigma Modulators,” IEEE Transactions on Information Theory, vol. 40, no. 3, pp. 848–859, May 1994.

P. Carbone and I. Galton, “Conversion Error in D/A Converters Employing Dynamic Element Matching,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1994, vol. 2, pp. 13–16.

I. Galton, “One-Bit Dithering in Delta-Sigma Modulator-Based D/A Conversion,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1993, pp. 1310–1313 vol. 2.

I. Galton, “Granular Quantization Noise in the First-Order Delta-Sigma Modulator,” IEEE Transactions on Information Theory, vol. 39, no. 6, pp. 1944–1956, Nov. 1993.

I. Galton and G. Zimmerman, “Combined RF Phase Extraction and Digitization,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1993, pp. 1104–1107 vol. 2.

I. Galton, “An Efficient Three-Point Arc Algorithm,” IEEE Computer Graphics and Applications, vol. 9, no. 6, pp. 44–49, Nov. 1989.

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