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J. Remple, “Inter-symbol Interference Mitigation in Dynamic Element Matching DACs,” Ph.D. dissertation, University of California, San Diego, 2021.

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E. Familier, “Spurious Tone Mitigation in Fractional-N Phase-Locked Loops,” Ph.D. dissertation, University of California, San Diego, 2016.

C. Venerus, “Delta-Sigma FDC Based Fractional-N PLLs with Multi-Rate Quantizing Dynamic Element Matching,” Ph.D. Dissertation, University of California, San Diego, 2013.

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N. Rakuljic, “A Generalized Tree-Structured DEM DAC and Enhanced Harmonic Distortion Correction in Pipelined ADCs,” Ph.D. dissertation, University of California, San Diego, 2012.

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G. Taylor, “Mostly Digital ADCs for Highly Scaled CMOS Processes,” Ph.D. dissertation, University of California, San Diego, 2011.

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K. Wang, “Spur Reduction Techniques for Fractional-N PLLs,” Ph.D. dissertation, University of California, San Diego, 2010.

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A. Panigada, “Harmonic Distortion Correction in Pipelined Analog to Digital Converters,” Ph.D. dissertation, University of California, San Diego, 2009.

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K. L. Chan, “High Speed, High Resolution Digital-to-Analog Converters,” Ph.D. dissertation, University of California, San Diego, 2007.

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J. Welz, “The Analysis and Design of Mismatch Shaping Digital-to-Analog Converters,” Ph.D. dissertation, University of California, San Diego, 2002.

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