The Integrated Signal Processing Group's research objective is to generate enabling technology for highly integrated, low-cost, low-power communication systems. The research involves the invention, development, analysis, and CMOS integrated circuit implementation of key communication system blocks such as analog-to-digital converters, digital-to-analog converters, fractional-N phase locked loops, and clock recovery systems. The emphasis of the research is on the development of digital signal processing techniques that mitigate the effects of non-ideal analog circuit behavior in mixed-signal (combined analog and digital) integrated circuits. The goal is to overcome present analog performance limitations imposed by IC processes optimized for digital circuitry.

In return for the ever increasing circuit densities offered by such IC processes, the amenability of the circuit components to conventional methods of processing analog signals has been largely sacrificed. However, it is now feasible to use large amounts of digital signal processing in concert with analog circuitry to compensate for analog component limitations. The group's research exploits this opportunity. The resulting circuits tend to blur the traditionally sharp analog-digital dividing lines in communication systems in order to reduce the precision requirements of the analog circuitry.

• Mismatch-shaping DACs for high-performance delta-sigma data converters
• Segmented dynamic element matching for Nyquist-rate, high-resolution DACs
• DAC noise cancellation and interstage gain error compensation techniques in pipelined ADCs
• Digital correction of analog non-linearity in pipelined ADCs
• Fractional-N phase-locked loop frequency synthesis
• Injection locking techniques for phase noise reduction in frequency synthesizers