Publications

K. Wang, A. Swaminathan, I. Galton, "Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL (Slides)", International Solid-State Circuits Conference, 2008.

A. Swaminathan, K. J. Wang, I. Galton, "A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation", Solid-State Circuits, IEEE Journal of, vol. 42, no. 12, December 2007.

A. Swaminathan, A. Panigada, E. Masry, I. Galton, "A digital requantizer with shaped requantization noise that remains well behaved after non-linear distortion", IEEE Transactions on Signal Processing, accepted for publication, vol. 55, no. 11, November 11, 2007.

K. L. Chan, J. Zhu, I. Galton, "A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquist band", Symposium on VLSI Circuits, Digest of Technical Papers, accepted for publication , June 14, 2007.

K. L. Chan, J. Zhu, I. Galton, "A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquist band", VLSI Circuits, 2007 IEEE Symposium on, June 14, 2007.

S. Pamarti, I. Galton, "LSB Dithering in MASH Delta–Sigma D/A Converters", Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 54, no. 4, April 2007.

S. Pamarti, J. Welz, I. Galton, "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators", Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 54, no. 3, March 2007.

A. Swaminathan, K. Wang, I. Galton, "A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation", ISSCC 2007 Digest of Technical Papers, 2007.

A. Panigada, I. Galton, "Digital Background Correction of Harmonic Distortion in Pipelined ADCs", Circuits and Systems - I: Regular Papers, IEEE Transactions on, vol. 53, no. 9, September 2006.

J. Rode, A. Swaminathan, I. Galton, P. M. Asbeck, "Fractional-N direct digital frequency synthesis with a 1-bit output", Microwave Symposium Digest, IEEE MTT-S International, June 2006.

K. L. Chan, I. Galton, "A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching", IEEE International Solid-State Circuits Conference, 2006.

J.L. Ceballos, I. Galton, G.C. Temes, "Stochastic analog-to-digital conversion", Circuits and Systems, 2005. 48th Midwest Symposium on, August 2005.

S. Pamarti, L. Jansson, I. Galton, "Addition to “A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation”", Solid-State Circuits, IEEE Journal of, vol. 40, no. 2, 2005.

M. Y. Li, I. Galton, L. E. Larson, P. M. Asbeck, "Nonlinearity estimation and spectral regrowth prediction of power amplifiers using correlation techniques", Wireless and Microwave Technology, 2005. WAMICON 2005. The 2005 IEEE Annual Conference, 2005.

E. Siragusa, I. Galton, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC", Solid-State Circuits, IEEE Journal of, vol. 39, no. 12, December 2004.

M. Y. Li, I. Galton, L. E. Larson, P. M. Asbeck, "Correlation techniques for estimation of amplifier nonlinearity", Radio and Wireless Conference, 2004 IEEE, September 2004.

Ye Sheng, I. Galton, "Techniques for phase noise suppression in recirculating DLLs", Solid-State Circuits, IEEE Journal of, vol. 39, no. 8, August 2004.

J. Welz, I. Galton, "A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter", Information Theory, IEEE Transactions on, vol. 50, no. 4, April 2004.

S. Pamarti, L. Jansson, I. Galton, "A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation", Solid-State Circuits, IEEE Journal of, vol. 39, no. 1, January 2004.

E. Siragusa, I. Galton, "A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC", Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, 2004.

S. Pamarti, I. Galton, "Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs", Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 50, no. 11, November 2003.

Ye Sheng, L. Jansson,I. Galton, "Techniques for in-band phase noise suppression in re-circulating DLLs", Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, September 2003.

S. Ye, L. Jansson, I. Galton, "A multiple-crystal interface PLL with VCO realignment to reduce phase noise", IEEE Journal of Solid-State Circuits, vol. 37, no. 12, December 2002.

J. Welz, I. Galton, "Necessary and sufficient conditions for mismatch shaping in a general class of multibit DACs", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 12, pp. 748-759, December 2002.

J. Keyzer, R. Uang, Y. Sugiyama, M. Iwamoto, I. Galton, P. M. Asbeck, "Generation of RF pulsewidth modulated microwave signals using delta-sigma modulation", Microwave Symposium Digest, 2002 IEEE MTT-S International, vol. 1, June 2002.

A. Fishov, E. Siragusa, J. Welz, E. Fogleman, I. Galton, "Segmented mismatch-shaping D/A conversion", Proc. of the IEEE International Symposium on Circuits and Systems, May 2002.

J. Welz, I. Galton, "A necessary and sufficient condition for mismatch shaping in multi-bit DACs", Proc. of the IEEE International Symposium on Circuits and Systems, May 2002.

P. Asbeck, I. Galton, K.-C. Wang, J. F. Jensen, A. K. Oki, C. T. M. Chang, "Digital signal processing-up to microwave frequencies", IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 3, pp. 900-909, March 2002, invited paper.

J. Grilo, I. Galton, K. Wang, R. Montemayor, "A 12 mW ADC delta-sigma modulator with 80dB of dynamic range integrated in a single-chip Bluetooth transceiver", IEEE Journal of Solid-State Circuits, vol. 37, no. 3, March 2002.

S. Ye, L. Jansson, I. Galton, "A multiple-crystal interface PLL with VCO realignment to reduce phase noise", IEEE International Solid-State Circuits Conference, pp. 78-79, 446, February 2002.

G. Chang, L. Jansson, K. Wang, J. Grilo, R. Montemayor, C. Hull, M. Lane, A. X. Estrada, M. Anderson, I. Galton, S. V. Kishore, "A direct-conversion single-chip radio-modem for Bluetooth", IEEE International Solid-State Circuits Conference, pp. 88-89, 448, February 2002.

I. Galton, "Delta-sigma data conversion in wireless transceivers", IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 302-316, January 2002, invited paper.

J. Welz, I. Galton, E. Fogleman, "Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 11, pp. 1014-1028, November 2001.

P. M. Asbeck, L. E. Larson, I. Galton, "Synergistic design of DSP and power amplifiers for wireless communications", IEEE Transactions on Microwave Theory and Techniques, vol. 49, no. 11, pp. 2163-2169, November 2001.

J. Grilo, I. Galton, K. Wang, R. Montemayor, "A 12 mW ADC delta-sigma modulator with 80dB of dynamic range integrated in A Single-Chip Bluetooth Transceiver", Proc. of the IEEE Custom Integrated Circuits Conference, pp. 23-26, May 2001.

J. Welz, I. Galton, "The mismatch-noise PSD from a tree-structured DAC in a second-order DS modulator with a midscale input", Proc. of the IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. Vol. 4, pp. 2625-2628, May 2001.

J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, P. Asbeck, "Digital generation of RF signals for wireless communications with band-pass delta-sigma modulation", Microwave Symposium Digest, IEEE MTT-S International, no. 2127-2130, May 2001.

E. Fogleman, J. Welz, I. Galton, "An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC", IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 339-348, March 2001.

E. Fogleman, I. Galton, "A digital common-mode rejection technique for differential analog-to-digital conversion", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 3, March 2001.

E. Fogleman, I. Galton, "A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 2, pp. 158-170, February 2001.

E. Fogleman, J. Welz, I. Galton, "An audio ADC Delta-Sigma modulator with 100 dB peak SINAD and 102 dB DR using a second-order mismatch-shaping DAC", Proc. of the IEEE Custom Integrated Circuits Conference, May 2000.

E. J. Siragusa, I Galton, "Gain error correction technique for pipelined analogue-to-digital converters", IEE Electronics Letters, vol. 36, no. 7, pp. 617-618, March 30, 2000.

I. Galton, "Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 3, pp. 185-196, March 2000.

E. Fogleman, I. Galton, W. Huff, H. T. Jensen, "A 3.3V single-poly CMOS audio ADC delta-sigma modulator with 98dB peak SINAD and 105dB peak SFDR", IEEE Journal of Solid State Circuits, vol. 35, no. 3, pp. 297-307, March 2000.

E. Fogleman, I. Galton, H.T. Jensen, "A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs", Proc. of the IEEE International Symposium on Circuits and Systems, June 1999.

E. Fogleman, I. Galton, H.T. Jensen, "An area-efficient differential input ADC with digital common mode rejection", Proc. of the IEEE International Symposium on Circuits and Systems, June 1999.

E. Fogleman, I. Galton, W. Huff, H.T. Jensen, "A 3.3V single-poly CMOS audio ADC delta-sigma modulator with 98 dB Peak SINAD", Proc. IEEE Custom Integrated Circuits Conference, May 1999.

I. Galton, W. Huff, P. Carbone, E. Siragusa, "A delta-sigma PLL for 14b 50kSample/s frequency-to-digital conversion of a 10 MHz FM signal", IEEE Journal of Solid State Circuits, vol. 33, no. 12, pp. 2042-2053, December 1998.

H.T. Jensen and I. Galton, "An analysis of the partial randomization dynamic element matching technique", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 12, pp. 1538-1549, December 1998.

H.T. Jensen, I. Galton, "A reduced-complexity mismatch-shaping DAC for delta-sigma data converters", Proc. IEEE Symposium on Circuits and Systems, vol. 1, pp. 504-507, May 1998.

W. Huff, I. Galton, "Nonuniform-to-uniform decimation for delta-sigma frequency-to-digital conversion", Proc. IEEE Symposium on Circuits and Systems, vol. 1, pp. 365-368, May 1998.

I. Galton, W. Huff, P. Carbone, E. Siragusa, "A delta-sigma PLL for 14b 50kSample/s frequency-to-digital conversion of a 10 MHz FM signal", IEEE International Solid-State Circuits Conference, vol. 41, pp. 366-367, February 1998.

H.T. Jensen and I. Galton, "A low-complexity dynamic element matching DAC for direct digital synthesis", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 1, pp. 13-27, January 1998.

E.T. King, A. Eshraghi, I. Galton, T.S. Fiez, "A Nyquist-rate delta-sigma A/D converter", IEEE Journal of Solid State Circuits, vol. 33, no. 1, pp. 45-52, January 1998.

I. Galton, "Spectral shaping of circuit errors in digital-to-analog converters", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 10, pp. 808-817, November 1997.

H.T. Jensen, I. Galton, "A performance analysis of the partial randomization dynamic element matching DAC architecture", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 9-12, June 1997.

H.T. Jensen, I. Galton, "Yield estimation of a first-order noise-shaping D/A converter", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 441-444, June 1997.

I. Galton and H.T. Jensen, "Oversampling parallel delta-sigma modulator A/D conversion", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 12, pp. 801-810, May 1996.

I. Galton, "Noise-shaping D/A converters for delta-sigma modulation", Proc. of the 1998 International Symposium on Circuits and Systems, vol. 1, May 1996.

I. Galton, H.T. Jensen, J.J. Rosenberg, D.A. Towne, "Clock distribution using coupled oscillators", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 3, pp. 217-220, May 1996.

H.T. Jensen, I. Galton, "A hardware-efficient DAC for direct digital synthesis", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 4, pp. 97-100, May 1996.

I. Galton and H.T. Jensen, "Delta-sigma modulator based A/D conversion without oversampling", IEEE Transactions on Circuits and Systems II: Analog to Digital Signal Processing, vol. 42, no. 12, pp. 773-784, December 1995.

I. Galton and P. Carbone, "A rigorous analysis of D/A conversion with dynamic element matching", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 12, pp. 763-772, December 1995.

I. Galton, "Analog-input digital phase-locked loops for precise frequency and phase demodulation", IEEE Transactions on Circuits and Systems II: Analog and Digital Processing, vol. 42, no. 10, pp. 621-630, November 1995.

H.T. Jensen, I. Galton, "A robust parallel delta-sigma A/D converter architecture", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1340-1343, May 1995.

I. Galton, "A practical second-order delta-sigma frequency-to-digital converter", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 5-8, May 1995.

E. King, F. Aram, T. Fiez, I. Galton, "Parallel delta-sigma A/D conversion", Proc. of the IEEE Custom Integrated Circuits Conference, pp. 503-506, May 1994.

I. Galton, "Higher-order delta-sigma frequency-to-digital conversion", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 5, pp. 441-444, May 1994.

P. Carbone, I. Galton, "Conversion error in D/A employing dynamic element matching", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 13-16, May 1994.

I. Galton, "Granular quantization noise in a class of delta-sigma modulators", IEEE Transactions on Information Theory, vol. 40, no. 3, pp. 848-859, 1994.

I. Galton, "Granular quantization noise in the first-order delta-sigma modulator", IEEE Transactions on Information Theory, vol. 39, no. 6, pp. 1944-1956, 1993.

I. Galton, G. Zimmerman, "Combined RF phase extraction and digitization", Proc. of the IEEE International Symposium on Circuits and Systems, 1993.

I. Galton, "One-bit dithering in delta-sigma modulator-based D/A conversion", Proc. of the IEEE International Symposium on Circuits and Systems, 1993.

I. Galton, "An efficient three point arc algorithm", IEEE Computer Graphics and Applications, vol. 9, no. 6, pp. 44-49, 1989.