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| Andrea Panigada |
Digital Background Calibration in Pipelined ADCs
Andrea Panigada (S’05) received the Laurea degree in electrical engineering from the University of Pavia, Pavia, Italy, in 1999. Since 2005, he has been working toward the Ph.D. degree at the University of California, San Diego (UCSD). From 2000 to 2004, he was a Design Engineer at the Studio di Microelettronica, Pavia, Italy, a Design Center founded by STMicroelectronics with the cooperation of the Electronic Department of the University of Pavia. There he conducted research in algorithms for the digital calibration of analog to digital converters and in the design of CMOS prototypes of sigma–delta and pipelined ADCs. In 2003, he spent one year as a Visiting Scholar at UCSD, where he worked with the Integrated Signal Processing Group (ISPG). He is currently with the ISPG. His research interests are in the field of mixed-signal integrated circuits and systems, including data converters. |
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| Last modified February 22, 2008 |
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